tools/arch/x86/include/asm/msr-index.h

Source file repositories/reference/linux-study-clean/tools/arch/x86/include/asm/msr-index.h

File Facts

System
Linux kernel
Corpus path
tools/arch/x86/include/asm/msr-index.h
Extension
.h
Size
50980 bytes
Lines
1310
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: implementation source
Status
source implementation candidate

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ASM_X86_MSR_INDEX_H
#define _ASM_X86_MSR_INDEX_H

#include <linux/bits.h>

/* CPU model specific register (MSR) numbers. */

/* x86-64 specific MSRs */
#define MSR_EFER		0xc0000080 /* extended feature register */
#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
#define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
#define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */

/* EFER bits: */
#define _EFER_SCE		0  /* SYSCALL/SYSRET */
#define _EFER_LME		8  /* Long mode enable */
#define _EFER_LMA		10 /* Long mode active (read-only) */
#define _EFER_NX		11 /* No execute enable */
#define _EFER_SVME		12 /* Enable virtualization */
#define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
#define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */
#define _EFER_TCE		15 /* Enable Translation Cache Extensions */
#define _EFER_AUTOIBRS		21 /* Enable Automatic IBRS */

#define EFER_SCE		(1<<_EFER_SCE)
#define EFER_LME		(1<<_EFER_LME)
#define EFER_LMA		(1<<_EFER_LMA)
#define EFER_NX			(1<<_EFER_NX)
#define EFER_SVME		(1<<_EFER_SVME)
#define EFER_LMSLE		(1<<_EFER_LMSLE)
#define EFER_FFXSR		(1<<_EFER_FFXSR)
#define EFER_TCE		(1<<_EFER_TCE)
#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)

/*
 * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc.
 * Most MSRs support/allow only a subset of memory types, but the values
 * themselves are common across all relevant MSRs.
 */
#define X86_MEMTYPE_UC		0ull	/* Uncacheable, a.k.a. Strong Uncacheable */
#define X86_MEMTYPE_WC		1ull	/* Write Combining */
/* RESERVED			2 */
/* RESERVED			3 */
#define X86_MEMTYPE_WT		4ull	/* Write Through */
#define X86_MEMTYPE_WP		5ull	/* Write Protected */
#define X86_MEMTYPE_WB		6ull	/* Write Back */
#define X86_MEMTYPE_UC_MINUS	7ull	/* Weak Uncacheabled (PAT only) */

/* FRED MSRs */
#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */
#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */
#define MSR_IA32_FRED_RSP2	0x1ce			/* Level 2 stack pointer */
#define MSR_IA32_FRED_RSP3	0x1cf			/* Level 3 stack pointer */
#define MSR_IA32_FRED_STKLVLS	0x1d0			/* Exception stack levels */
#define MSR_IA32_FRED_SSP0	MSR_IA32_PL0_SSP	/* Level 0 shadow stack pointer */
#define MSR_IA32_FRED_SSP1	0x1d1			/* Level 1 shadow stack pointer */
#define MSR_IA32_FRED_SSP2	0x1d2			/* Level 2 shadow stack pointer */
#define MSR_IA32_FRED_SSP3	0x1d3			/* Level 3 shadow stack pointer */
#define MSR_IA32_FRED_CONFIG	0x1d4			/* Entrypoint and interrupt stack level */

/* Intel MSRs. Some also available on other CPUs */
#define MSR_TEST_CTRL				0x00000033
#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29
#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)

#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
#define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
#define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
#define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
#define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
#define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
#define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */
#define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
#define SPEC_CTRL_BHI_DIS_S_SHIFT	10	   /* Disable Branch History Injection behavior */
#define SPEC_CTRL_BHI_DIS_S		BIT(SPEC_CTRL_BHI_DIS_S_SHIFT)

/* A mask for bits which the kernel toggles when controlling mitigations */
#define SPEC_CTRL_MITIGATIONS_MASK	(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
							| SPEC_CTRL_RRSBA_DIS_S \
							| SPEC_CTRL_BHI_DIS_S)

#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
#define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
#define PRED_CMD_SBPB			BIT(7)	   /* Selective Branch Prediction Barrier */

Annotation

Implementation Notes