tools/perf/Documentation/perf-c2c.txt

Source file repositories/reference/linux-study-clean/tools/perf/Documentation/perf-c2c.txt

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Linux kernel
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tools/perf/Documentation/perf-c2c.txt
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.txt
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Support Tooling And Documentation
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tools
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Support Tooling And Documentation: documentation
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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perf-c2c(1)
===========

NAME
----
perf-c2c - Shared Data C2C/HITM Analyzer.

SYNOPSIS
--------
[verse]
'perf c2c record' [<options>] <command>
'perf c2c record' [<options>] \-- [<record command options>] <command>
'perf c2c report' [<options>]

DESCRIPTION
-----------
C2C stands for Cache To Cache.

The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
you to track down the cacheline contentions.

On Intel, the tool is based on load latency and precise store facility events
provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to
sample load and store operations, therefore hardware and kernel support is
required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
statistical nature of Arm SPE sampling, not every memory operation will be
sampled.

These events provide:
  - memory address of the access
  - type of the access (load and store details)
  - latency (in cycles) of the load access

The c2c tool provide means to record this data and report back access details
for cachelines with highest contention - highest number of HITM accesses.

The basic workflow with this tool follows the standard record/report phase.
User uses the record command to record events data and report command to
display it.


RECORD OPTIONS
--------------
-e::
--event=::
	Select the PMU event. Use 'perf c2c record -e list'
	to list available events.

-v::
--verbose::
	Be more verbose (show counter open errors, etc).

-l::
--ldlat::
	Configure mem-loads latency. Supported on Intel, Arm64 and some AMD
	processors. Ignored on other archs.

	On supported AMD processors:
	- /sys/bus/event_source/devices/ibs_op/caps/ldlat file contains '1'.
	- Supported latency values are 128 to 2048 (both inclusive).
	- Latency value which is a multiple of 128 incurs a little less profiling
	  overhead compared to other values.
	- Load latency filtering is disabled by default.

-k::
--all-kernel::
	Configure all used events to run in kernel space.

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