tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json
Extension
.json
Size
5359 bytes
Lines
60
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "BR_MIS_PRED"
    },
    {
        "ArchStdEvent": "BR_PRED"
    },
    {
        "ArchStdEvent": "BR_IMMED_SPEC"
    },
    {
        "ArchStdEvent": "BR_RETURN_SPEC"
    },
    {
        "ArchStdEvent": "BR_INDIRECT_SPEC"
    },
    {
        "PublicDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
        "EventCode": "0xC9",
        "EventName": "BR_COND_PRED",
        "BriefDescription": "Predicted conditional branch executed. This event counts when any branch that the conditional predictor can predict is retired. This event still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
    },
    {
        "PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off",
        "EventCode": "0xCA",
        "EventName": "BR_INDIRECT_MIS_PRED",
        "BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that the Branch Target Address Cache (BTAC) can predict is retired and has mispredicted either the condition or the address. This event still counts when branch prediction is disabled due to the MMU being off"
    },
    {
        "PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
        "EventCode": "0xCB",
        "EventName": "BR_INDIRECT_ADDR_MIS_PRED",
        "BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts when any indirect branch that the BTAC can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
    },
    {
        "PublicDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count",
        "EventCode": "0xCC",
        "EventName": "BR_COND_MIS_PRED",
        "BriefDescription": "Conditional branch mispredicted. This event counts when any branch that the conditional predictor can predict is retired and has mispredicted the condition. This event still counts when branch prediction is disabled due to the MMU being off. Conditional indirect branches that correctly predict the condition but mispredict the address do not count"
    },
    {
        "PublicDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
        "EventCode": "0xCD",
        "EventName": "BR_INDIRECT_ADDR_PRED",
        "BriefDescription": "Indirect branch with predicted address executed. This event counts when any indirect branch that the BTAC can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
    },
    {
        "PublicDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off",
        "EventCode": "0xCE",
        "EventName": "BR_RETURN_ADDR_PRED",
        "BriefDescription": "Procedure return with predicted address executed. This event counts when any procedure return that the call-return stack can predict is retired, was taken, and correctly predicted the condition. This event still counts when branch prediction is disabled due to the MMU being off"
    },
    {
        "PublicDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off",
        "EventCode": "0xCF",
        "EventName": "BR_RETURN_ADDR_MIS_PRED",
        "BriefDescription": "Procedure return mispredicted due to address miscompare. This event counts when any procedure return that the call-return stack can predict is retired, was taken, correctly predicted the condition, and has mispredicted the address. This event still counts when branch prediction is disabled due to the MMU being off"
    }
]

Annotation

Implementation Notes