tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json
Extension
.json
Size
7693 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "STALL_FRONTEND"
    },
    {
        "ArchStdEvent": "STALL_BACKEND"
    },
    {
        "ArchStdEvent": "STALL"
    },
    {
        "ArchStdEvent": "STALL_SLOT_BACKEND"
    },
    {
        "ArchStdEvent": "STALL_SLOT_FRONTEND"
    },
    {
        "ArchStdEvent": "STALL_SLOT"
    },
    {
        "PublicDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed",
        "EventCode": "0xE1",
        "EventName": "STALL_FRONTEND_CACHE",
        "BriefDescription": "No operation issued due to the frontend, cache miss. This event counts every cycle that the Data Processing Unit (DPU) instruction queue is empty and there is an instruction cache miss being processed"
    },
    {
        "PublicDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed",
        "EventCode": "0xE2",
        "EventName": "STALL_FRONTEND_TLB",
        "BriefDescription": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty and there is an instruction L1 TLB miss being processed"
    },
    {
        "PublicDescription": "No operation issued due to the frontend, pre-decode error",
        "EventCode": "0xE3",
        "EventName": "STALL_FRONTEND_PDERR",
        "BriefDescription": "No operation issued due to the frontend, pre-decode error"
    },
    {
        "PublicDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
        "EventCode": "0xE4",
        "EventName": "STALL_BACKEND_ILOCK",
        "BriefDescription": "No operation issued due to the backend interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
    },
    {
        "PublicDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
        "EventCode": "0xE5",
        "EventName": "STALL_BACKEND_ILOCK_ADDR",
        "BriefDescription": "No operation issued due to the backend, address interlock. This event counts every cycle where the issue of an operation is stalled and there is an interlock on an address operand. This type of interlock is caused by a load/store instruction waiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
    },
    {
        "PublicDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
        "EventCode": "0xE6",
        "EventName": "STALL_BACKEND_ILOCK_VPU",
        "BriefDescription": "No operation issued due to the backend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interlock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
    },
    {
        "PublicDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
        "EventCode": "0xE7",
        "EventName": "STALL_BACKEND_LD",
        "BriefDescription": "No operation issued due to the backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
    },
    {
        "PublicDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
        "EventCode": "0xE8",
        "EventName": "STALL_BACKEND_ST",
        "BriefDescription": "No operation issued due to the backend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
    },
    {
        "PublicDescription": "No operation issued due to the backend, load, cache miss. This event counts every cycle where there is a stall in the Wr stage due to a load that is waiting on data. The event counts for stalls that are caused by missing the cache or where the data is Non-cacheable",
        "EventCode": "0xE9",

Annotation

Implementation Notes