tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json
Extension
.json
Size
2692 bytes
Lines
45
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "STALL_FRONTEND"
    },
    {
        "ArchStdEvent": "STALL_BACKEND"
    },
    {
        "PublicDescription": "A linefill caused an instruction side stall",
        "EventCode": "0xC0",
        "EventName": "LF_STALL",
        "BriefDescription": "A linefill caused an instruction side stall"
    },
    {
        "PublicDescription": "A translation table walk caused an instruction side stall",
        "EventCode": "0xC1",
        "EventName": "PTW_STALL",
        "BriefDescription": "A translation table walk caused an instruction side stall"
    },
    {
        "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
        "EventCode": "0xD3",
        "EventName": "D_LSU_SLOT_FULL",
        "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
    },
    {
        "PublicDescription": "Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty",
        "EventCode": "0xD8",
        "EventName": "LS_IQ_FULL",
        "BriefDescription": "Duration for which all slots in the load-store issue queue are busy. This event counts the cycles where all slots in the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty"
    },
    {
        "PublicDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty",
        "EventCode": "0xD9",
        "EventName": "DP_IQ_FULL",
        "BriefDescription": "Duration for which all slots in the data processing issue queue are busy. This event counts the cycles where all slots in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty"
    },
    {
        "PublicDescription": "Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW",
        "EventCode": "0xDA",
        "EventName": "DE_IQ_FULL",
        "BriefDescription": "Duration for which all slots in the data engine issue queue are busy. This event is set every time that the data engine rename has at least one valid instruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_instr is LOW"
    }
]

Annotation

Implementation Notes