tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json
Extension
.json
Size
6843 bytes
Lines
170
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
        "ArchStdEvent": "L1I_CACHE_REFILL"
    },
    {
        "PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
        "ArchStdEvent": "L1I_TLB_REFILL"
    },
    {
        "PublicDescription": "This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.",
        "ArchStdEvent": "L1D_CACHE_REFILL"
    },
    {
        "PublicDescription": "This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.",
        "ArchStdEvent": "L1D_CACHE"
    },
    {
        "PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
        "ArchStdEvent": "L1D_TLB_REFILL"
    },
    {
        "PublicDescription": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.",
        "ArchStdEvent": "L1I_CACHE"
    },
    {
        "PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.",
        "ArchStdEvent": "L1D_CACHE_WB"
    },
    {
        "PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
        "ArchStdEvent": "L2D_CACHE"
    },
    {
        "PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
        "ArchStdEvent": "L2D_CACHE_REFILL"
    },
    {
        "PublicDescription": "This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted",
        "ArchStdEvent": "L2D_CACHE_WB"
    },
    {
        "PublicDescription": "This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.",
        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
    },
    {
        "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.",
        "ArchStdEvent": "L1D_TLB",
        "BriefDescription": "Level 1 data TLB access."
    },
    {
        "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled.",
        "ArchStdEvent": "L1I_TLB",
        "BriefDescription": "Level 1 instruction TLB access"
    },
    {
        "PublicDescription": "This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2",
        "ArchStdEvent": "L3D_CACHE_ALLOCATE",
        "BriefDescription": "Allocation without refill"
    },
    {
        "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions.",
        "ArchStdEvent": "L3D_CACHE_REFILL",
        "BriefDescription": "Attributable Level 3 unified cache refill."
    },
    {
        "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU.",
        "ArchStdEvent": "L3D_CACHE",
        "BriefDescription": "Attributable Level 3 unified cache access."
    },

Annotation

Implementation Notes