tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json
Extension
.json
Size
1196 bytes
Lines
23
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "L3D_CACHE_ALLOCATE",
        "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores."
    },
    {
        "ArchStdEvent": "L3D_CACHE_REFILL",
        "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache."
    },
    {
        "ArchStdEvent": "L3D_CACHE",
        "PublicDescription": "Counts level 3 cache accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
    },
    {
        "ArchStdEvent": "L3D_CACHE_RD",
        "PublicDescription": "Counts level 3 cache accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses."
    },
    {
        "ArchStdEvent": "L3D_CACHE_LMISS_RD",
        "PublicDescription": "Counts any cache line refill into the level 3 cache from memory read operations that incurred additional latency."
    }
]

Annotation

Implementation Notes