tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json
Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json
File Facts
- System
- Linux kernel
- Corpus path
tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/metrics.json- Extension
.json- Size
- 25414 bytes
- Lines
- 458
- Domain
- Support Tooling And Documentation
- Bucket
- tools
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
[
{
"ArchStdEvent": "backend_bound"
},
{
"MetricName": "backend_busy_bound",
"MetricExpr": "STALL_BACKEND_BUSY / STALL_BACKEND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to issue queues being full to accept operations for execution.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_cache_l1d_bound",
"MetricExpr": "STALL_BACKEND_L1D / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 1 data cache misses.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_cache_l2d_bound",
"MetricExpr": "STALL_BACKEND_MEM / (STALL_BACKEND_L1D + STALL_BACKEND_MEM) * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by level 2 data cache misses.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_core_bound",
"MetricExpr": "STALL_BACKEND_CPUBOUND / STALL_BACKEND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints not related to instruction fetch latency issues caused by memory access components.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_core_rename_bound",
"MetricExpr": "STALL_BACKEND_RENAME / STALL_BACKEND_CPUBOUND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend as the rename unit registers are unavailable.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_mem_bound",
"MetricExpr": "STALL_BACKEND_MEMBOUND / STALL_BACKEND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend core resource constraints related to memory access latency issues caused by memory access components.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_mem_cache_bound",
"MetricExpr": "(STALL_BACKEND_L1D + STALL_BACKEND_MEM) / STALL_BACKEND_MEMBOUND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory latency issues caused by data cache misses.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_mem_store_bound",
"MetricExpr": "STALL_BACKEND_ST / STALL_BACKEND_MEMBOUND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the frontend due to memory write pending caused by stores stalled in the pre-commit stage.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_mem_tlb_bound",
"MetricExpr": "STALL_BACKEND_TLB / STALL_BACKEND_MEMBOUND * 100",
"BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by data TLB misses.",
"MetricGroup": "Topdown_Backend",
"ScaleUnit": "1percent of cycles"
},
{
"MetricName": "backend_stalled_cycles",
"MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100",
Annotation
- Atlas domain: Support Tooling And Documentation / tools.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.