tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json

File Facts

System

Linux kernel

Corpus path

tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json

Extension

.json

Size

1986 bytes

Lines

114

Domain

Support Tooling And Documentation

Bucket

tools

Inferred role

Support Tooling And Documentation: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

[
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_TLB_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_WR"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_TLB_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_WR"
    },
    {
        "ArchStdEvent": "BUS_ACCESS_RD"
    },
    {
        "ArchStdEvent": "BUS_ACCESS_WR"
    },
    {
        "ArchStdEvent": "MEM_ACCESS_RD"
    },
    {
        "ArchStdEvent": "MEM_ACCESS_WR"
    },
    {
        "ArchStdEvent": "UNALIGNED_LD_SPEC"
    },
    {
        "ArchStdEvent": "UNALIGNED_ST_SPEC"
    },

Annotation

• Atlas domain: Support Tooling And Documentation / tools.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.