tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json
Extension
.json
Size
5458 bytes
Lines
123
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "EventCode": "0x0182",
        "EventName": "LD_COMP_WAIT_L1_MISS",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access."
    },
    {
        "EventCode": "0x0183",
        "EventName": "LD_COMP_WAIT_L1_MISS_EX",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access."
    },
    {
        "EventCode": "0x0184",
        "EventName": "LD_COMP_WAIT",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access."
    },
    {
        "EventCode": "0x0185",
        "EventName": "LD_COMP_WAIT_EX",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access."
    },
    {
        "EventCode": "0x0186",
        "EventName": "LD_COMP_WAIT_PFP_BUSY",
        "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port."
    },
    {
        "EventCode": "0x0187",
        "EventName": "LD_COMP_WAIT_PFP_BUSY_EX",
        "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation."
    },
    {
        "EventCode": "0x0188",
        "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF",
        "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction."
    },
    {
        "EventCode": "0x0189",
        "EventName": "EU_COMP_WAIT",
        "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction."
    },
    {
        "EventCode": "0x018A",
        "EventName": "FL_COMP_WAIT",
        "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction."
    },
    {
        "EventCode": "0x018B",
        "EventName": "BR_COMP_WAIT",
        "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction."
    },
    {
        "EventCode": "0x018C",
        "EventName": "ROB_EMPTY",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty."
    },
    {
        "EventCode": "0x018D",
        "EventName": "ROB_EMPTY_STQ_BUSY",
        "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full."
    },
    {
        "EventCode": "0x018E",
        "EventName": "WFE_WFI_CYCLE",
        "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction."
    },
    {
        "EventCode": "0x018F",
        "EventName": "RETENTION_CYCLE",
        "BriefDescription": "This event counts every cycle that the instruction unit is halted by the RETENTION state."

Annotation

Implementation Notes