tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l1d_cache.json
Extension
.json
Size
4841 bytes
Lines
114
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "L1D_CACHE_REFILL",
        "BriefDescription": "This event counts operations that cause a refill of the L1D cache. See L1D_CACHE_REFILL of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L1D_CACHE",
        "BriefDescription": "This event counts operations that cause a cache access to the L1D cache. See L1D_CACHE of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB",
        "BriefDescription": "This event counts every write-back of data from the L1D cache. See L1D_CACHE_WB of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L1D_CACHE_LMISS_RD",
        "BriefDescription": "This event counts operations that cause a refill of the L1D cache that incurs additional latency."
    },
    {
        "ArchStdEvent": "L1D_CACHE_RD",
        "BriefDescription": "This event counts L1D CACHE caused by read access."
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR",
        "BriefDescription": "This event counts L1D CACHE caused by write access."
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access."
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access."
    },
    {
        "EventCode": "0x0200",
        "EventName": "L1D_CACHE_DM",
        "BriefDescription": "This event counts L1D_CACHE caused by demand access."
    },
    {
        "EventCode": "0x0201",
        "EventName": "L1D_CACHE_DM_RD",
        "BriefDescription": "This event counts L1D_CACHE caused by demand read access."
    },
    {
        "EventCode": "0x0202",
        "EventName": "L1D_CACHE_DM_WR",
        "BriefDescription": "This event counts L1D_CACHE caused by demand write access."
    },
    {
        "EventCode": "0x0208",
        "EventName": "L1D_CACHE_REFILL_DM",
        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
    },
    {
        "EventCode": "0x0209",
        "EventName": "L1D_CACHE_REFILL_DM_RD",
        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access."
    },
    {
        "EventCode": "0x020A",
        "EventName": "L1D_CACHE_REFILL_DM_WR",
        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand write access."
    },
    {
        "EventCode": "0x020D",
        "EventName": "L1D_CACHE_BTC",
        "BriefDescription": "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data cache, causing a coherence access to outside of the Level 1 caches of this PE."
    },
    {
        "ArchStdEvent": "L1D_CACHE_MISS",

Annotation

Implementation Notes