tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/l2_cache.json
Extension
.json
Size
6852 bytes
Lines
161
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "L2D_CACHE",
        "BriefDescription": "This event counts operations that cause a cache access to the L2 cache. See L2D_CACHE of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL",
        "BriefDescription": "This event counts operations that cause a refill of the L2 cache. See L2D_CACHE_REFILL of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB",
        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA."
    },
    {
        "ArchStdEvent": "L2I_TLB_REFILL",
        "BriefDescription": "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_TLB_REFILL of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L2I_TLB",
        "BriefDescription": "This event counts operations that cause a TLB access to the L2I TLB. See L2I_TLB of ARMv9 Reference Manual for more information."
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD",
        "BriefDescription": "This event counts L2D_CACHE caused by read access."
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR",
        "BriefDescription": "This event counts L2D_CACHE caused by write access."
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD",
        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access."
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR",
        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access."
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
        "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace."
    },
    {
        "EventCode": "0x0300",
        "EventName": "L2D_CACHE_DM",
        "BriefDescription": "This event counts L2D_CACHE caused by demand access."
    },
    {
        "EventCode": "0x0301",
        "EventName": "L2D_CACHE_DM_RD",
        "BriefDescription": "This event counts L2D_CACHE caused by demand read access."
    },
    {
        "EventCode": "0x0302",
        "EventName": "L2D_CACHE_DM_WR",
        "BriefDescription": "This event counts L2D_CACHE caused by demand write access."
    },
    {
        "EventCode": "0x0305",
        "EventName": "L2D_CACHE_HWPRF_ADJACENT",
        "BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch."
    },
    {
        "EventCode": "0x0308",
        "EventName": "L2D_CACHE_REFILL_DM",
        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
    },
    {
        "EventCode": "0x0309",
        "EventName": "L2D_CACHE_REFILL_DM_RD",
        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand read access."

Annotation

Implementation Notes