tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/fujitsu/monaka/stall.json
Extension
.json
Size
5220 bytes
Lines
95
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "STALL_FRONTEND",
        "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because there are no operations available to issue for this PE from the frontend."
    },
    {
        "ArchStdEvent": "STALL_BACKEND",
        "BriefDescription": "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operation."
    },
    {
        "ArchStdEvent": "STALL",
        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit."
    },
    {
        "ArchStdEvent": "STALL_SLOT_BACKEND",
        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the backend."
    },
    {
        "ArchStdEvent": "STALL_SLOT_FRONTEND",
        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to the frontend."
    },
    {
        "ArchStdEvent": "STALL_SLOT",
        "BriefDescription": "This event counts every cycle that no instruction or operation Slot was dispatched from decode unit."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_MEM",
        "BriefDescription": "This event counts every cycle that no instruction was dispatched from decode unit due to memory stall."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_MEMBOUND",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when no instructions are delivered from the memory system."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_L1I",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the first level of instruction cache."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_L2I",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the second level of instruction cache."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_MEM",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the last level of instruction cache within the PE clock domain or a non-cacheable instruction fetch in progress."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_CPUBOUND",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND when the frontend is stalled on a frontend processor resource, not including memory."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_FLOW",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is stalled on unavailability of prediction flow resources."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_FLUSH",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is recovering from a pipeline flush."
    },
    {
        "ArchStdEvent": "STALL_FRONTEND_RENAME",
        "BriefDescription": "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_MEMBOUND",
        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND when the backend is waiting for a memory access to complete."
    },
    {
        "ArchStdEvent": "STALL_BACKEND_L1D",
        "BriefDescription": "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L1D cache."
    },
    {

Annotation

Implementation Notes