tools/perf/pmu-events/arch/arm64/nvidia/t410/l1i_cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/nvidia/t410/l1i_cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/nvidia/t410/l1i_cache.json
Extension
.json
Size
7741 bytes
Lines
115
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "L1I_CACHE_REFILL",
        "PublicDescription": "This event counts cache line refills in the L1 I-cache caused by a missed instruction fetch (demand, hardware prefetch, and software preload accesses). Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once."
    },
    {
        "ArchStdEvent": "L1I_CACHE",
        "PublicDescription": "This event counts instruction fetches (demand, hardware prefetch, and software preload accesses) which access the L1 Instruction Cache. Instruction Cache accesses caused by cache maintenance operations are not counted."
    },
    {
        "ArchStdEvent": "L1I_CACHE_LMISS",
        "PublicDescription": "This event counts cache line refills into the L1 I-cache, that incurred additional latency.\nCounts the same as L1I_CACHE_REFILL in this CPU."
    },
    {
        "ArchStdEvent": "L1I_CACHE_RD",
        "PublicDescription": "This event counts demand instruction fetches which access the L1 I-cache."
    },
    {
        "ArchStdEvent": "L1I_CACHE_PRFM",
        "PublicDescription": "This event counts instruction fetches generated by software preload or prefetch instructions which access the L1 I-cache."
    },
    {
        "ArchStdEvent": "L1I_CACHE_HWPRF",
        "PublicDescription": "This event counts instruction fetches which access the L1 I-cache generated by the hardware prefetcher."
    },
    {
        "ArchStdEvent": "L1I_CACHE_REFILL_PRFM",
        "PublicDescription": "This event counts cache line refills in the L1 I-cache caused by a missed instruction fetch generated by software preload or prefetch instructions. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once."
    },
    {
        "ArchStdEvent": "L1I_CACHE_REFILL_HWPRF",
        "PublicDescription": "This event counts each hardware prefetch access counted by L1I_CACHE_HWPRF that causes a refill of the Level 1I-cache from outside of the L1 I-cache."
    },
    {
        "ArchStdEvent": "L1I_CACHE_HIT_RD",
        "PublicDescription": "This event counts demand instruction fetches that access the L1 I-cache and hit in the L1 I-cache."
    },
    {
        "ArchStdEvent": "L1I_CACHE_HIT_RD_FPRF",
        "PublicDescription": "This event counts each demand fetch first hit counted by L1I_CACHE_HIT_RD where the cache line was fetched in response to a software preload or by a hardware prefetcher. That is, the L1I_CACHE_REFILL_PRF event was generated when the cache line was fetched into the cache.\nOnly the first hit by a demand access is counted. After this event is generated for a cache line, the event is not generated again for the same cache line while it remains in the cache."
    },
    {
        "ArchStdEvent": "L1I_CACHE_HIT",
        "PublicDescription": "This event counts instruction fetches that access the L1 I-cache (demand, hardware prefetch, and software preload accesses) and hit in the L1 I-cache. I-cache accesses caused by cache maintenance operations are not counted."
    },
    {
        "ArchStdEvent": "L1I_CACHE_HIT_PRFM",
        "PublicDescription": "This event counts instruction fetches generated by software preload or prefetch instructions that access the L1 I-cache and hit in the L1 I-cache."
    },
    {
        "ArchStdEvent": "L1I_LFB_HIT_RD",
        "PublicDescription": "This event counts demand instruction fetches that access the L1 I-cache and hit in a line that is in the process of being loaded into the L1 I-cache."
    },
    {
        "EventCode": "0x0174",
        "EventName": "L1I_HWPRF_REQ_DROP",
        "PublicDescription": "L1 I-cache hardware prefetch dropped."
    },
    {
        "EventCode": "0x01e3",
        "EventName": "L1I_CACHE_REFILL_RD",
        "PublicDescription": "L1 I-cache refill, Read.\nThis event counts demand instruction fetch that causes a refill of the L1 I-cache of this PE, from outside of this cache."
    },
    {
        "EventCode": "0x01ea",
        "EventName": "L1I_CFC_ENTRIES",
        "PublicDescription": "This event counts the CFC (Cache Fill Control) entries.\nThe CFC is the fill buffer for I-cache."
    },
    {
        "EventCode": "0x01ef",

Annotation

Implementation Notes