tools/perf/pmu-events/arch/arm64/nvidia/t410/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/nvidia/t410/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/nvidia/t410/memory.json
Extension
.json
Size
4386 bytes
Lines
47
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "MEM_ACCESS",
        "PublicDescription": "This event counts memory accesses issued by the CPU load/store unit, where those accesses are issued due to load or store operations. This event counts memory accesses regardless of whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions.\nMemory accesses generated by the following instructions or activity are not counted: instruction fetches, cache maintenance instructions, translation table walks or prefetches, memory prefetch operations. This event counts the sum of the following events:\nMEM_ACCESS_RD and\nMEM_ACCESS_WR."
    },
    {
        "ArchStdEvent": "MEMORY_ERROR",
        "PublicDescription": "This event counts any detected correctable or uncorrectable physical memory errors (ECC or parity) in protected CPU RAMs. On the Core, this event counts errors in the caches (including data and tag RAMs). Any detected memory error (from either a speculative and abandoned access, or an architecturally executed access) is counted.\nNote that errors are only detected when the actual protected memory is accessed by an operation."
    },
    {
        "ArchStdEvent": "REMOTE_ACCESS",
        "PublicDescription": "This event counts each external bus read access that causes an access to a remote device. That is, a socket that does not contain the PE."
    },
    {
        "ArchStdEvent": "MEM_ACCESS_RD",
        "PublicDescription": "This event counts memory accesses issued by the CPU due to Load operations. This event counts any memory Load access, no matter whether the data is received from any level of cache hierarchy or external memory. This event also counts atomic Load operations. If memory accesses are broken up by the Load/Store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions.\nThe following instructions are not counted:\n1) Instruction fetches,\n2) Cache maintenance instructions,\n3) Translation table walks or prefetches,\n4) Memory prefetch operations.\nThis event is a subset of the MEM_ACCESS event but the event only counts memory-Read operations."
    },
    {
        "ArchStdEvent": "MEM_ACCESS_WR",
        "PublicDescription": "This event counts memory accesses issued by the CPU due to Store operations. This event counts any memory Store access, no matter whether the data is located in any level of cache or external memory. This event also counts atomic Load and Store operations. If memory accesses are broken up by the Load/Store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions."
    },
    {
        "ArchStdEvent": "LDST_ALIGN_LAT",
        "PublicDescription": "This event counts the number of memory Read and Write accesses in a cycle that incurred additional latency due to the alignment of the address and the size of data being accessed, which results in a store crossing a single cache line.\nThis event is implemented as the sum of the following events on this CPU:\nLD_ALIGN_LAT and\nST_ALIGN_LAT."
    },
    {
        "ArchStdEvent": "LD_ALIGN_LAT",
        "PublicDescription": "This event counts the number of memory Read accesses in a cycle that incurred additional latency due to the alignment of the address and size of data being accessed, which results in a load crossing a single cache line."
    },
    {
        "ArchStdEvent": "ST_ALIGN_LAT",
        "PublicDescription": "This event counts the number of memory Write accesses in a cycle that incurred additional latency due to the alignment of the address and size of data being accessed."
    },
    {
        "ArchStdEvent": "INST_FETCH_PERCYC",
        "PublicDescription": "This event counts number of instruction fetches outstanding per cycle, which will provide an average latency of instruction fetch."
    },
    {
        "ArchStdEvent": "MEM_ACCESS_RD_PERCYC",
        "PublicDescription": "This event counts the number of outstanding Loads or memory Read accesses per cycle."
    },
    {
        "ArchStdEvent": "INST_FETCH",
        "PublicDescription": "This event counts instruction memory accesses that the PE makes."
    }
]

Annotation

Implementation Notes