tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/nvidia/t410/metrics.json
Extension
.json
Size
40193 bytes
Lines
723
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "MetricName": "backend_bound",
        "MetricExpr": "100 * (STALL_SLOT_BACKEND / CPU_SLOT)",
        "BriefDescription": "This metric is the percentage of total slots that were stalled due to resource constraints in the backend of the processor.",
        "ScaleUnit": "1percent of slots",
        "MetricGroup": "TopdownL1"
    },
    {
        "MetricName": "backend_busy_bound",
        "MetricExpr": "100 * (STALL_BACKEND_BUSY / STALL_BACKEND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to issue queues being full to accept operations for execution.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_cache_l1d_bound",
        "MetricExpr": "100 * (STALL_BACKEND_L1D / (STALL_BACKEND_L1D + STALL_BACKEND_MEM))",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by L1 D-cache misses.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_cache_l2d_bound",
        "MetricExpr": "100 * (STALL_BACKEND_MEM / (STALL_BACKEND_L1D + STALL_BACKEND_MEM))",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by L2 D-cache misses.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_core_bound",
        "MetricExpr": "100 * (STALL_BACKEND_CPUBOUND / STALL_BACKEND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend Core resource constraints not related to instruction fetch latency issues caused by memory access components.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_core_rename_bound",
        "MetricExpr": "100 * (STALL_BACKEND_RENAME / STALL_BACKEND_CPUBOUND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend as the rename unit registers are unavailable.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_mem_bound",
        "MetricExpr": "100 * (STALL_BACKEND_MEMBOUND / STALL_BACKEND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to backend Core resource constraints related to memory access latency issues caused by memory access components.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_mem_cache_bound",
        "MetricExpr": "100 * ((STALL_BACKEND_L1D + STALL_BACKEND_MEM) / STALL_BACKEND_MEMBOUND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory latency issues caused by D-cache misses.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_mem_store_bound",
        "MetricExpr": "100 * (STALL_BACKEND_ST / STALL_BACKEND_MEMBOUND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory Write pending caused by Stores stalled in the pre-commit stage.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"
    },
    {
        "MetricName": "backend_mem_tlb_bound",
        "MetricExpr": "100 * (STALL_BACKEND_TLB / STALL_BACKEND_MEMBOUND)",
        "BriefDescription": "This metric is the percentage of total cycles stalled in the backend due to memory access latency issues caused by Data TLB misses.",
        "ScaleUnit": "1percent of cycles",
        "MetricGroup": "Topdown_Backend"

Annotation

Implementation Notes