tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json
Extension
.json
Size
29544 bytes
Lines
643
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "ArchStdEvent": "SW_INCR",
        "PublicDescription": "This event counts software writes to the PMSWINC_EL0 (software PMU increment) register. The PMSWINC_EL0 register is a manually updated counter for use by application software.\nThis event could be used to measure any user program event, such as accesses to a particular data structure (by writing to the PMSWINC_EL0 register each time the data structure is accessed).\nTo use the PMSWINC_EL0 register and event, developers must insert instructions that write to the PMSWINC_EL0 register into the source code.\nSince the SW_INCR event records writes to the PMSWINC_EL0 register, there is no need to do a Read/Increment/Write sequence to the PMSWINC_EL0 register."
    },
    {
        "ArchStdEvent": "TRB_WRAP",
        "PublicDescription": "This event is generated each time the trace buffer current Write pointer is wrapped to the trace buffer base pointer."
    },
    {
        "ArchStdEvent": "TRCEXTOUT0",
        "PublicDescription": "Trace unit external output 0."
    },
    {
        "ArchStdEvent": "TRCEXTOUT1",
        "PublicDescription": "Trace unit external output 1."
    },
    {
        "ArchStdEvent": "TRCEXTOUT2",
        "PublicDescription": "Trace unit external output 2."
    },
    {
        "ArchStdEvent": "TRCEXTOUT3",
        "PublicDescription": "Trace unit external output 3."
    },
    {
        "ArchStdEvent": "CTI_TRIGOUT4",
        "PublicDescription": "Cross-trigger Interface output trigger 4."
    },
    {
        "ArchStdEvent": "CTI_TRIGOUT5",
        "PublicDescription": "Cross-trigger Interface output trigger 5."
    },
    {
        "ArchStdEvent": "CTI_TRIGOUT6",
        "PublicDescription": "Cross-trigger Interface output trigger 6."
    },
    {
        "ArchStdEvent": "CTI_TRIGOUT7",
        "PublicDescription": "Cross-trigger Interface output trigger 7."
    },
    {
        "EventCode": "0x00e1",
        "EventName": "L1I_PRFM_REQ_DROP",
        "PublicDescription": "L1 I-cache software prefetch dropped."
    },
    {
        "EventCode": "0x0100",
        "EventName": "L1_PF_REFILL",
        "PublicDescription": "L1 prefetch requests, refilled to L1 cache."
    },
    {
        "EventCode": "0x0120",
        "EventName": "FLUSH",
        "PublicDescription": "This event counts both the CT flush and BX flush. The BR_MIS_PRED counts the BX flushes. So the FLUSH-BR_MIS_PRED gives the CT flushes."
    },
    {
        "EventCode": "0x0121",
        "EventName": "FLUSH_MEM",
        "PublicDescription": "Flushes due to memory hazards. This only includes CT flushes."
    },
    {
        "EventCode": "0x0122",
        "EventName": "FLUSH_BAD_BRANCH",
        "PublicDescription": "Flushes due to bad predicted branch. This only includes CT flushes."
    },
    {
        "EventCode": "0x0123",
        "EventName": "FLUSH_STDBYPASS",
        "PublicDescription": "Flushes due to bad predecode. This only includes CT flushes."

Annotation

Implementation Notes