tools/perf/pmu-events/arch/powerpc/power10/marked.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power10/marked.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power10/marked.json
Extension
.json
Size
12040 bytes
Lines
273
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x10132",
    "EventName": "PM_MRK_INST_ISSUED",
    "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
  },
  {
    "EventCode": "0x10134",
    "EventName": "PM_MRK_ST_DONE_L2",
    "BriefDescription": "Marked store completed in L2."
  },
  {
    "EventCode": "0x1C142",
    "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x1C144",
    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
  },
  {
    "EventCode": "0x1D15C",
    "EventName": "PM_MRK_DTLB_MISS_1G",
    "BriefDescription": "Marked Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x1F150",
    "EventName": "PM_MRK_ST_L2_CYC",
    "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
  },
  {
    "EventCode": "0x101E0",
    "EventName": "PM_MRK_INST_DISP",
    "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
  },
  {
    "EventCode": "0x101E2",
    "EventName": "PM_MRK_BR_TAKEN_CMPL",
    "BriefDescription": "Marked Branch Taken instruction completed."
  },
  {
    "EventCode": "0x101E4",
    "EventName": "PM_MRK_L1_ICACHE_MISS",
    "BriefDescription": "Marked instruction suffered an instruction cache miss."
  },
  {
    "EventCode": "0x101EA",
    "EventName": "PM_MRK_L1_RELOAD_VALID",
    "BriefDescription": "Marked demand reload."
  },
  {
    "EventCode": "0x20114",
    "EventName": "PM_MRK_L2_RC_DISP",
    "BriefDescription": "Marked instruction RC dispatched in L2."
  },
  {
    "EventCode": "0x2011C",
    "EventName": "PM_MRK_NTF_CYC",
    "BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete)."
  },
  {
    "EventCode": "0x20130",
    "EventName": "PM_MRK_INST_DECODED",
    "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
  },
  {
    "EventCode": "0x20132",
    "EventName": "PM_MRK_DFU_ISSUE",
    "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."

Annotation

Implementation Notes