tools/perf/pmu-events/arch/powerpc/power10/pipeline.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power10/pipeline.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power10/pipeline.json
Extension
.json
Size
22897 bytes
Lines
508
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x10004",
    "EventName": "PM_EXEC_STALL_TRANSLATION",
    "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."
  },
  {
    "EventCode": "0x10006",
    "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",
    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason."
  },
  {
    "EventCode": "0x1000C",
    "EventName": "PM_LSU_LD0_FIN",
    "BriefDescription": "LSU Finished an internal operation in LD0 port."
  },
  {
    "EventCode": "0x1000E",
    "EventName": "PM_MMA_ISSUED",
    "BriefDescription": "MMA instruction issued."
  },
  {
    "EventCode": "0x10012",
    "EventName": "PM_LSU_ST0_FIN",
    "BriefDescription": "LSU Finished an internal operation in ST0 port."
  },
  {
    "EventCode": "0x10014",
    "EventName": "PM_LSU_ST4_FIN",
    "BriefDescription": "LSU Finished an internal operation in ST4 port."
  },
  {
    "EventCode": "0x10018",
    "EventName": "PM_IC_DEMAND_CYC",
    "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
  },
  {
    "EventCode": "0x10028",
    "EventName": "PM_NTC_FLUSH",
    "BriefDescription": "The instruction was flushed after becoming next-to-complete (NTC)."
  },
  {
    "EventCode": "0x10038",
    "EventName": "PM_DISP_STALL_TRANSLATION",
    "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."
  },
  {
    "EventCode": "0x1003A",
    "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",
    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
  },
  {
    "EventCode": "0x1003C",
    "EventName": "PM_EXEC_STALL_DMISS_L2L3",
    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
  },
  {
    "EventCode": "0x10058",
    "EventName": "PM_EXEC_STALL_FIN_AT_DISP",
    "BriefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
  },
  {
    "EventCode": "0x1005A",
    "EventName": "PM_FLUSH_MPRED",
    "BriefDescription": "A flush occurred due to a mispredicted branch. Includes target and direction."
  },
  {
    "EventCode": "0x1C05A",
    "EventName": "PM_DERAT_MISS_2M",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

Annotation

Implementation Notes