tools/perf/pmu-events/arch/powerpc/power8/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power8/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power8/cache.json
Extension
.json
Size
10240 bytes
Lines
177
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x4c048",
    "EventName": "PM_DATA_FROM_DL2L3_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x3c048",
    "EventName": "PM_DATA_FROM_DL2L3_SHR",
    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x3c04c",
    "EventName": "PM_DATA_FROM_DL4",
    "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x1c042",
    "EventName": "PM_DATA_FROM_L2",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x200fe",
    "EventName": "PM_DATA_FROM_L2MISS",
    "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
    "PublicDescription": ""
  },
  {
    "EventCode": "0x1c04e",
    "EventName": "PM_DATA_FROM_L2MISS_MOD",
    "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x3c040",
    "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x4c040",
    "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x2c040",
    "EventName": "PM_DATA_FROM_L2_MEPF",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x1c040",
    "EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x4c042",
    "EventName": "PM_DATA_FROM_L3",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
    "PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
  },
  {
    "EventCode": "0x300fe",
    "EventName": "PM_DATA_FROM_L3MISS",

Annotation

Implementation Notes