tools/perf/pmu-events/arch/powerpc/power9/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power9/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power9/cache.json
Extension
.json
Size
4743 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x300F4",
    "EventName": "PM_THRD_CONC_RUN_INST",
    "BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
  },
  {
    "EventCode": "0x1E056",
    "EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
    "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
  },
  {
    "EventCode": "0x4D016",
    "EventName": "PM_CMPLU_STALL_FXLONG",
    "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
  },
  {
    "EventCode": "0x2D016",
    "EventName": "PM_CMPLU_STALL_FXU",
    "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
  },
  {
    "EventCode": "0x4D12A",
    "EventName": "PM_MRK_DATA_FROM_RL4_CYC",
    "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
  },
  {
    "EventCode": "0x1003C",
    "EventName": "PM_CMPLU_STALL_DMISS_L2L3",
    "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
  },
  {
    "EventCode": "0x4C014",
    "EventName": "PM_CMPLU_STALL_LMQ_FULL",
    "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
  },
  {
    "EventCode": "0x14048",
    "EventName": "PM_INST_FROM_ON_CHIP_CACHE",
    "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
  },
  {
    "EventCode": "0x4D014",
    "EventName": "PM_CMPLU_STALL_LOAD_FINISH",
    "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
  },
  {
    "EventCode": "0x2404A",
    "EventName": "PM_INST_FROM_RL4",
    "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
  },
  {
    "EventCode": "0x1404A",
    "EventName": "PM_INST_FROM_RL2L3_SHR",
    "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
  },
  {
    "EventCode": "0x401EA",
    "EventName": "PM_THRESH_EXC_128",
    "BriefDescription": "Threshold counter exceeded a value of 128"
  },
  {
    "EventCode": "0x400F6",
    "EventName": "PM_BR_MPRED_CMPL",
    "BriefDescription": "Number of Branch Mispredicts"
  },
  {
    "EventCode": "0x2F140",
    "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"

Annotation

Implementation Notes