tools/perf/pmu-events/arch/powerpc/power9/frontend.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power9/frontend.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power9/frontend.json
Extension
.json
Size
14556 bytes
Lines
357
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x25044",
    "EventName": "PM_IPTEG_FROM_L31_MOD",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
  },
  {
    "EventCode": "0x101E8",
    "EventName": "PM_THRESH_EXC_256",
    "BriefDescription": "Threshold counter exceed a count of 256"
  },
  {
    "EventCode": "0x4504E",
    "EventName": "PM_IPTEG_FROM_L3MISS",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request"
  },
  {
    "EventCode": "0x1006A",
    "EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
    "BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it"
  },
  {
    "EventCode": "0x4E016",
    "EventName": "PM_CMPLU_STALL_LSAQ_ARB",
    "BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch"
  },
  {
    "EventCode": "0x1001A",
    "EventName": "PM_LSU_SRQ_FULL_CYC",
    "BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource"
  },
  {
    "EventCode": "0x1E15E",
    "EventName": "PM_MRK_L2_TM_REQ_ABORT",
    "BriefDescription": "TM abort"
  },
  {
    "EventCode": "0x34052",
    "EventName": "PM_INST_SYS_PUMP_MPRED",
    "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch"
  },
  {
    "EventCode": "0x20114",
    "EventName": "PM_MRK_L2_RC_DISP",
    "BriefDescription": "Marked Instruction RC dispatched in L2"
  },
  {
    "EventCode": "0x4C044",
    "EventName": "PM_DATA_FROM_L31_ECO_MOD",
    "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load"
  },
  {
    "EventCode": "0x1C044",
    "EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
    "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load"
  },
  {
    "EventCode": "0x44050",
    "EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
    "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
  },
  {
    "EventCode": "0x30154",
    "EventName": "PM_MRK_FAB_RSP_DCLAIM",
    "BriefDescription": "Marked store had to do a dclaim"
  },
  {
    "EventCode": "0x30014",
    "EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
    "BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe"

Annotation

Implementation Notes