tools/perf/pmu-events/arch/powerpc/power9/pipeline.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
Extension
.json
Size
23113 bytes
Lines
532
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x4D04C",
    "EventName": "PM_DFU_BUSY",
    "BriefDescription": "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity"
  },
  {
    "EventCode": "0x100F6",
    "EventName": "PM_IERAT_RELOAD",
    "BriefDescription": "Number of I-ERAT reloads"
  },
  {
    "EventCode": "0x201E2",
    "EventName": "PM_MRK_LD_MISS_L1",
    "BriefDescription": "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
  },
  {
    "EventCode": "0x40010",
    "EventName": "PM_PMC3_OVERFLOW",
    "BriefDescription": "Overflow from counter 3"
  },
  {
    "EventCode": "0x1005A",
    "EventName": "PM_CMPLU_STALL_DFLONG",
    "BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle"
  },
  {
    "EventCode": "0x4D140",
    "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
    "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
  },
  {
    "EventCode": "0x3F14C",
    "EventName": "PM_MRK_DPTEG_FROM_DL4",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x1E040",
    "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x24052",
    "EventName": "PM_FXU_IDLE",
    "BriefDescription": "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle"
  },
  {
    "EventCode": "0x1E054",
    "EventName": "PM_CMPLU_STALL",
    "BriefDescription": "Nothing completed and ICT not empty"
  },
  {
    "EventCode": "0x2",
    "EventName": "PM_INST_CMPL",
    "BriefDescription": "Number of PowerPC Instructions that completed."
  },
  {
    "EventCode": "0x3D058",
    "EventName": "PM_VSU_DP_FSQRT_FDIV",
    "BriefDescription": "vector versions of fdiv,fsqrt"
  },
  {
    "EventCode": "0x10006",
    "EventName": "PM_DISP_HELD",
    "BriefDescription": "Dispatch Held"
  },
  {
    "EventCode": "0x200F8",
    "EventName": "PM_EXT_INT",
    "BriefDescription": "external interrupt"

Annotation

Implementation Notes