tools/perf/pmu-events/arch/powerpc/power9/pmc.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power9/pmc.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power9/pmc.json
Extension
.json
Size
4989 bytes
Lines
118
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x20036",
    "EventName": "PM_BR_2PATH",
    "BriefDescription": "Branches that are not strongly biased"
  },
  {
    "EventCode": "0x40056",
    "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
    "BriefDescription": "Local memory above threshold for LSU medium"
  },
  {
    "EventCode": "0x40118",
    "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
    "BriefDescription": "Combined Intervention event"
  },
  {
    "EventCode": "0x4F148",
    "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x301E8",
    "EventName": "PM_THRESH_EXC_64",
    "BriefDescription": "Threshold counter exceeded a value of 64"
  },
  {
    "EventCode": "0x4E04E",
    "EventName": "PM_DPTEG_FROM_L3MISS",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x40050",
    "EventName": "PM_SYS_PUMP_MPRED_RTY",
    "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
  },
  {
    "EventCode": "0x1F14E",
    "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x4D018",
    "EventName": "PM_CMPLU_STALL_BRU",
    "BriefDescription": "Completion stall due to a Branch Unit"
  },
  {
    "EventCode": "0x45052",
    "EventName": "PM_4FLOP_CMPL",
    "BriefDescription": "4 FLOP instruction completed"
  },
  {
    "EventCode": "0x3D142",
    "EventName": "PM_MRK_DATA_FROM_LMEM",
    "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
  },
  {
    "EventCode": "0x4C01E",
    "EventName": "PM_CMPLU_STALL_CRYPTO",
    "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
  },
  {
    "EventCode": "0x3000C",
    "EventName": "PM_FREQ_DOWN",
    "BriefDescription": "Power Management: Below Threshold B"
  },
  {
    "EventCode": "0x4D128",
    "EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
    "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"

Annotation

Implementation Notes