tools/perf/pmu-events/arch/powerpc/power9/translation.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/powerpc/power9/translation.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/powerpc/power9/translation.json
Extension
.json
Size
9853 bytes
Lines
228
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventCode": "0x1E",
    "EventName": "PM_CYC",
    "BriefDescription": "Processor cycles"
  },
  {
    "EventCode": "0x30010",
    "EventName": "PM_PMC2_OVERFLOW",
    "BriefDescription": "Overflow from counter 2"
  },
  {
    "EventCode": "0x3C046",
    "EventName": "PM_DATA_FROM_L21_SHR",
    "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
  },
  {
    "EventCode": "0x4D05C",
    "EventName": "PM_DP_QP_FLOP_CMPL",
    "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
  },
  {
    "EventCode": "0x4E04C",
    "EventName": "PM_DPTEG_FROM_DMEM",
    "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x20016",
    "EventName": "PM_ST_FIN",
    "BriefDescription": "Store finish count. Includes speculative activity"
  },
  {
    "EventCode": "0x1504A",
    "EventName": "PM_IPTEG_FROM_RL2L3_SHR",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
  },
  {
    "EventCode": "0x40132",
    "EventName": "PM_MRK_LSU_FIN",
    "BriefDescription": "lsu marked instr PPC finish"
  },
  {
    "EventCode": "0x3C05C",
    "EventName": "PM_CMPLU_STALL_VFXU",
    "BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
  },
  {
    "EventCode": "0x30066",
    "EventName": "PM_LSU_FIN",
    "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
  },
  {
    "EventCode": "0x2011C",
    "EventName": "PM_MRK_NTC_CYC",
    "BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
  },
  {
    "EventCode": "0x3E048",
    "EventName": "PM_DPTEG_FROM_DL2L3_SHR",
    "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  },
  {
    "EventCode": "0x2E018",
    "EventName": "PM_CMPLU_STALL_VFXLONG",
    "BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
  },
  {
    "EventCode": "0x1C04E",
    "EventName": "PM_DATA_FROM_L2MISS_MOD",
    "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"

Annotation

Implementation Notes