tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json

File Facts

System

Linux kernel

Corpus path

tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json

Extension

.json

Size

3074 bytes

Lines

128

Domain

Support Tooling And Documentation

Bucket

tools

Inferred role

Support Tooling And Documentation: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

[
	{
		"EventCode": "0x10",
		"EventName": "cycle_count",
		"BriefDescription": "Cycle count"
	},
	{
		"EventCode": "0x20",
		"EventName": "inst_count",
		"BriefDescription": "Retired instruction count"
	},
	{
		"EventCode": "0x30",
		"EventName": "int_load_inst",
		"BriefDescription": "Integer load instruction count"
	},
	{
		"EventCode": "0x40",
		"EventName": "int_store_inst",
		"BriefDescription": "Integer store instruction count"
	},
	{
		"EventCode": "0x50",
		"EventName": "atomic_inst",
		"BriefDescription": "Atomic instruction count"
	},
	{
		"EventCode": "0x60",
		"EventName": "sys_inst",
		"BriefDescription": "System instruction count"
	},
	{
		"EventCode": "0x70",
		"EventName": "int_compute_inst",
		"BriefDescription": "Integer computational instruction count"
	},
	{
		"EventCode": "0x80",
		"EventName": "condition_br",
		"BriefDescription": "Conditional branch instruction count"
	},
	{
		"EventCode": "0x90",
		"EventName": "taken_condition_br",
		"BriefDescription": "Taken conditional branch instruction count"
	},
	{
		"EventCode": "0xA0",
		"EventName": "jal_inst",
		"BriefDescription": "JAL instruction count"
	},
	{
		"EventCode": "0xB0",
		"EventName": "jalr_inst",
		"BriefDescription": "JALR instruction count"
	},
	{
		"EventCode": "0xC0",
		"EventName": "ret_inst",
		"BriefDescription": "Return instruction count"
	},
	{
		"EventCode": "0xD0",
		"EventName": "control_trans_inst",
		"BriefDescription": "Control transfer instruction count"
	},
	{
		"EventCode": "0xE0",
		"EventName": "ex9_inst",
		"BriefDescription": "EXEC.IT instruction count"

Annotation

• Atlas domain: Support Tooling And Documentation / tools.
• Implementation status: atlas-only.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.