tools/perf/pmu-events/arch/s390/cf_z17/extended.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/s390/cf_z17/extended.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/s390/cf_z17/extended.json
Extension
.json
Size
25491 bytes
Lines
542
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "DTLB2_WRITES",
		"BriefDescription": "DTLB2 Writes",
		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "DTLB2_MISSES",
		"BriefDescription": "DTLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "CRSTE_1MB_WRITES",
		"BriefDescription": "One Megabyte CRSTE writes",
		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "132",
		"EventName": "DTLB2_GPAGE_WRITES",
		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "134",
		"EventName": "ITLB2_WRITES",
		"BriefDescription": "ITLB2 Writes",
		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "ITLB2_MISSES",
		"BriefDescription": "ITLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "TLB2_PTE_WRITES",
		"BriefDescription": "TLB2 Page Table Entry Writes",
		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "TLB2_CRSTE_WRITES",
		"BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "139",
		"EventName": "TLB2_ENGINES_BUSY",
		"BriefDescription": "TLB2 Engines Busy",
		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."

Annotation

Implementation Notes