tools/perf/pmu-events/arch/s390/cf_z196/extended.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/s390/cf_z196/extended.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/s390/cf_z196/extended.json
Extension
.json
Size
7033 bytes
Lines
171
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "L1D_L2_SOURCED_WRITES",
		"BriefDescription": "L1D L2 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from the Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "L1I_L2_SOURCED_WRITES",
		"BriefDescription": "L1I L2 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "DTLB1_MISSES",
		"BriefDescription": "DTLB1 Misses",
		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "ITLB1_MISSES",
		"BriefDescription": "ITLB1 Misses",
		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "133",
		"EventName": "L2C_STORES_SENT",
		"BriefDescription": "L2C Stores Sent",
		"PublicDescription": "Incremented by one for every store sent to Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "134",
		"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Book L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-3 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
		"BriefDescription": "L1D On-Book L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "136",
		"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
		"BriefDescription": "L1I On-Book L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Book L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-4 cache."

Annotation

Implementation Notes