tools/perf/pmu-events/arch/s390/cf_zec12/extended.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
Extension
.json
Size
10918 bytes
Lines
248
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "DTLB1_MISSES",
		"BriefDescription": "DTLB1 Misses",
		"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "ITLB1_MISSES",
		"BriefDescription": "ITLB1 Misses",
		"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "L1D_L2I_SOURCED_WRITES",
		"BriefDescription": "L1D L2I Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "L1I_L2I_SOURCED_WRITES",
		"BriefDescription": "L1I L2I Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "132",
		"EventName": "L1D_L2D_SOURCED_WRITES",
		"BriefDescription": "L1D L2D Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "133",
		"EventName": "DTLB1_WRITES",
		"BriefDescription": "DTLB1 Writes",
		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "L1D_LMEM_SOURCED_WRITES",
		"BriefDescription": "L1D Local Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "L1I_LMEM_SOURCED_WRITES",
		"BriefDescription": "L1I Local Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "139",
		"EventName": "DTLB1_HPAGE_WRITES",
		"BriefDescription": "DTLB1 One-Megabyte Page Writes",
		"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."

Annotation

Implementation Notes