tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json
Extension
.json
Size
6838 bytes
Lines
209
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts every 64B read  request entering the Memory Controller 0 to DRAM (sum of all channels).",
        "Counter": "0",
        "EventCode": "0xff",
        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).",
        "UMask": "0x20",
        "Unit": "imc_free_running_0"
    },
    {
        "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "Counter": "1",
        "EventCode": "0xff",
        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x30",
        "Unit": "imc_free_running_0"
    },
    {
        "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).",
        "Counter": "3",
        "EventCode": "0xff",
        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).",
        "UMask": "0x20",
        "Unit": "imc_free_running_1"
    },
    {
        "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "Counter": "4",
        "EventCode": "0xff",
        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "UMask": "0x30",
        "Unit": "imc_free_running_1"
    },
    {
        "BriefDescription": "ACT command for a read request sent to DRAM",
        "Counter": "0,1,2,3,4",
        "EventCode": "0x24",
        "EventName": "UNC_M_ACT_COUNT_RD",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "ACT command sent to DRAM",
        "Counter": "0,1,2,3,4",
        "EventCode": "0x26",
        "EventName": "UNC_M_ACT_COUNT_TOTAL",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "ACT command for a write request sent to DRAM",
        "Counter": "0,1,2,3,4",
        "EventCode": "0x25",
        "EventName": "UNC_M_ACT_COUNT_WR",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read CAS command sent to DRAM",
        "Counter": "0,1,2,3,4",
        "EventCode": "0x22",
        "EventName": "UNC_M_CAS_COUNT_RD",
        "PerPkg": "1",
        "Unit": "iMC"

Annotation

Implementation Notes