tools/perf/pmu-events/arch/x86/alderlaken/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/alderlaken/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/alderlaken/cache.json
Extension
.json
Size
30568 bytes
Lines
630
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.HIT",
        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH",
        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
        "SampleAfterValue": "200003",
        "UMask": "0x38"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
        "SampleAfterValue": "200003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
        "SampleAfterValue": "200003",

Annotation

Implementation Notes