tools/perf/pmu-events/arch/x86/amdzen1/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen1/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen1/cache.json
Extension
.json
Size
12698 bytes
Lines
336
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventName": "ic_fw32",
    "EventCode": "0x80",
    "BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)."
  },
  {
    "EventName": "ic_fw32_miss",
    "EventCode": "0x81",
    "BriefDescription": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
  },
  {
    "EventName": "ic_cache_fill_l2",
    "EventCode": "0x82",
    "BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
  },
  {
    "EventName": "ic_cache_fill_sys",
    "EventCode": "0x83",
    "BriefDescription": "The number of 64 byte instruction cache line fulfilled from system memory or another cache."
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_hit",
    "EventCode": "0x84",
    "BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
  },
  {
    "EventName": "bp_l1_tlb_miss_l2_miss",
    "EventCode": "0x85",
    "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
  },
  {
    "EventName": "bp_snp_re_sync",
    "EventCode": "0x86",
    "BriefDescription": "The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event."
  },
  {
    "EventName": "ic_fetch_stall.ic_stall_any",
    "EventCode": "0x87",
    "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).",
    "UMask": "0x04"
  },
  {
    "EventName": "ic_fetch_stall.ic_stall_dq_empty",
    "EventCode": "0x87",
    "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.",
    "UMask": "0x02"
  },
  {
    "EventName": "ic_fetch_stall.ic_stall_back_pressure",
    "EventCode": "0x87",
    "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
    "UMask": "0x01"
  },
  {
    "EventName": "ic_cache_inval.l2_invalidating_probe",
    "EventCode": "0x8c",
    "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
    "UMask": "0x02"
  },
  {
    "EventName": "ic_cache_inval.fill_invalidated",
    "EventCode": "0x8c",
    "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
    "UMask": "0x01"
  },
  {
    "EventName": "bp_tlb_rel",
    "EventCode": "0x99",
    "BriefDescription": "The number of ITLB reload requests."

Annotation

Implementation Notes