tools/perf/pmu-events/arch/x86/amdzen1/core.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen1/core.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen1/core.json
Extension
.json
Size
5945 bytes
Lines
126
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventName": "ex_ret_instr",
    "EventCode": "0xc0",
    "BriefDescription": "Retired Instructions."
  },
  {
    "EventName": "ex_ret_cops",
    "EventCode": "0xc1",
    "BriefDescription": "Retired Uops.",
    "PublicDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
  },
  {
    "EventName": "ex_ret_brn",
    "EventCode": "0xc2",
    "BriefDescription": "Retired Branch Instructions.",
    "PublicDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
  },
  {
    "EventName": "ex_ret_brn_misp",
    "EventCode": "0xc3",
    "BriefDescription": "Retired Branch Instructions Mispredicted.",
    "PublicDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
  },
  {
    "EventName": "ex_ret_brn_tkn",
    "EventCode": "0xc4",
    "BriefDescription": "Retired Taken Branch Instructions.",
    "PublicDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
  },
  {
    "EventName": "ex_ret_brn_tkn_misp",
    "EventCode": "0xc5",
    "BriefDescription": "Retired Taken Branch Instructions Mispredicted.",
    "PublicDescription": "The number of retired taken branch instructions that were mispredicted."
  },
  {
    "EventName": "ex_ret_brn_far",
    "EventCode": "0xc6",
    "BriefDescription": "Retired Far Control Transfers.",
    "PublicDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
  },
  {
    "EventName": "ex_ret_brn_resync",
    "EventCode": "0xc7",
    "BriefDescription": "Retired Branch Resyncs.",
    "PublicDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
  },
  {
    "EventName": "ex_ret_near_ret",
    "EventCode": "0xc8",
    "BriefDescription": "Retired Near Returns.",
    "PublicDescription": "The number of near return instructions (RET or RET Iw) retired."
  },
  {
    "EventName": "ex_ret_near_ret_mispred",
    "EventCode": "0xc9",
    "BriefDescription": "Retired Near Returns Mispredicted.",
    "PublicDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
    "EventName": "ex_ret_brn_ind_misp",
    "EventCode": "0xca",
    "BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.sse_instr",
    "EventCode": "0xcb",
    "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
    "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",

Annotation

Implementation Notes