tools/perf/pmu-events/arch/x86/amdzen2/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen2/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen2/cache.json
Extension
.json
Size
13668 bytes
Lines
362
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventName": "l2_request_g1.rd_blk_l",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch).",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_request_g1.rd_blk_x",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_request_g1.ls_rd_blk_c_s",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_request_g1.cacheable_ic_read",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_request_g1.change_to_x",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.",
    "UMask": "0x08"
  },
  {
    "EventName": "l2_request_g1.prefetch_l2_cmd",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_request_g1.l2_hw_pf",
    "EventCode": "0x60",
    "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_request_g1.group2",
    "EventCode": "0x60",
    "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
    "UMask": "0x01"
  },
  {
    "EventName": "l2_request_g1.all_no_prefetch",
    "EventCode": "0x60",
    "UMask": "0xf9"
  },
  {
    "EventName": "l2_request_g2.group1",
    "EventCode": "0x61",
    "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g1 (PMCx060).",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized",
    "EventCode": "0x61",
    "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized_nc",
    "EventCode": "0x61",
    "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.",

Annotation

Implementation Notes