tools/perf/pmu-events/arch/x86/amdzen4/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen4/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen4/memory.json
Extension
.json
Size
6095 bytes
Lines
175
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventName": "ls_bad_status2.stli_other",
    "EventCode": "0x24",
    "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dispatch.ld_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_dispatch.store_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_dispatch.ld_st_dispatch",
    "EventCode": "0x29",
    "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_stlf",
    "EventCode": "0x35",
    "BriefDescription": "Store-to-load-forward (STLF) hits."
  },
  {
    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
    "EventCode": "0x37",
    "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
    "UMask": "0x01"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
    "UMask": "0x02"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
    "UMask": "0x04"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
    "UMask": "0x08"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
    "UMask": "0x10"
  },
  {
    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
    "EventCode": "0x45",
    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",

Annotation

Implementation Notes