tools/perf/pmu-events/arch/x86/amdzen4/recommended.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen4/recommended.json
Extension
.json
Size
20150 bytes
Lines
419
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "MetricName": "branch_misprediction_ratio",
    "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
    "MetricGroup": "branch_prediction",
    "ScaleUnit": "100%"
  },
  {
    "EventName": "all_data_cache_accesses",
    "EventCode": "0x29",
    "BriefDescription": "All data cache accesses.",
    "UMask": "0x07"
  },
  {
    "MetricName": "all_l2_cache_accesses",
    "BriefDescription": "All L2 cache accesses.",
    "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_accesses_from_l1_ic_misses",
    "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
    "MetricExpr": "l2_request_g1.cacheable_ic_read",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_accesses_from_l1_dc_misses",
    "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
    "MetricExpr": "l2_request_g1.all_dc",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_accesses_from_l2_hwpf",
    "BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher.",
    "MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "all_l2_cache_misses",
    "BriefDescription": "All L2 cache misses.",
    "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_misses_from_l1_ic_miss",
    "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
    "MetricExpr": "l2_cache_req_stat.ic_fill_miss",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_misses_from_l1_dc_miss",
    "BriefDescription": "L2 cache misses from L1 data cache misses.",
    "MetricExpr": "l2_cache_req_stat.ls_rd_blk_c",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_misses_from_l2_hwpf",
    "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
    "MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "all_l2_cache_hits",
    "BriefDescription": "All L2 cache hits.",
    "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
    "MetricGroup": "l2_cache"
  },
  {
    "MetricName": "l2_cache_hits_from_l1_ic_miss",

Annotation

Implementation Notes