tools/perf/pmu-events/arch/x86/amdzen5/recommended.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen5/recommended.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen5/recommended.json
Extension
.json
Size
24624 bytes
Lines
458
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "MetricName": "branch_misprediction_rate",
    "BriefDescription": "Execution-time branch misprediction rate (non-speculative).",
    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
    "MetricGroup": "branch_prediction",
    "ScaleUnit": "1per_branch"
  },
  {
    "MetricName": "all_data_cache_accesses_pti",
    "BriefDescription": "All data cache accesses per thousand instructions.",
    "MetricExpr": "ls_dispatch.all / instructions",
    "MetricGroup": "l1_dcache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "all_l2_cache_accesses_pti",
    "BriefDescription": "All L2 cache accesses per thousand instructions.",
    "MetricExpr": "(l2_request_g1.all_no_prefetch + l2_pf_hit_l2.l2_hwpf + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_accesses_from_l1_ic_misses_pti",
    "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch) per thousand instructions.",
    "MetricExpr": "l2_request_g1.cacheable_ic_read / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_accesses_from_l1_dc_misses_pti",
    "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch) per thousand instructions.",
    "MetricExpr": "l2_request_g1.all_dc / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_accesses_from_l2_hwpf_pti",
    "BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher per thousand instructions.",
    "MetricExpr": "(l2_pf_hit_l2.l1_dc_l2_hwpf + l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "all_l2_cache_misses_pti",
    "BriefDescription": "All L2 cache misses per thousand instructions.",
    "MetricExpr": "(l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.l2_hwpf + l2_pf_miss_l2_l3.l2_hwpf) / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_misses_from_l1_ic_miss_pti",
    "BriefDescription": "L2 cache misses from L1 instruction cache misses per thousand instructions.",
    "MetricExpr": "l2_cache_req_stat.ic_fill_miss / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_misses_from_l1_dc_miss_pti",
    "BriefDescription": "L2 cache misses from L1 data cache misses per thousand instructions.",
    "MetricExpr": "l2_cache_req_stat.ls_rd_blk_c / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"
  },
  {
    "MetricName": "l2_cache_misses_from_l2_hwpf_pti",
    "BriefDescription": "L2 cache misses from L2 cache hardware prefetcher per thousand instructions.",
    "MetricExpr": "(l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf + l2_pf_miss_l2_l3.l1_dc_l2_hwpf) / instructions",
    "MetricGroup": "l2_cache",
    "ScaleUnit": "1e3per_1k_instr"

Annotation

Implementation Notes