tools/perf/pmu-events/arch/x86/amdzen6/l2-cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/amdzen6/l2-cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/amdzen6/l2-cache.json
Extension
.json
Size
12253 bytes
Lines
327
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
  {
    "EventName": "l2_request_g1.group2",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
    "UMask": "0x01"
  },
  {
    "EventName": "l2_request_g1.l2_hwpf",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests from hardware prefetchers to prefetch directly into L2 (hit or miss).",
    "UMask": "0x02"
  },
  {
    "EventName": "l2_request_g1.prefetch_l2_cmd",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests to prefetch directly into L2.",
    "UMask": "0x04"
  },
  {
    "EventName": "l2_request_g1.cacheable_ic_read",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for instruction cache reads.",
    "UMask": "0x10"
  },
  {
    "EventName": "l2_request_g1.ls_rd_blk_c_s",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache shared reads.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_request_g1.rd_blk_x",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache stores.",
    "UMask": "0x40"
  },
  {
    "EventName": "l2_request_g1.rd_blk_l",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests for data cache reads (includes hardware and software prefetches).",
    "UMask": "0x80"
  },
  {
    "EventName": "l2_request_g1.dc_all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of common types from data cache (includes prefetches).",
    "UMask": "0xe0"
  },
  {
    "EventName": "l2_request_g1.no_pf_all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of common types not including prefetches.",
    "UMask": "0xf1"
  },
  {
    "EventName": "l2_request_g1.all",
    "EventCode": "0x60",
    "BriefDescription": "L2 cache requests of all types.",
    "UMask": "0xf7"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized_nc",
    "EventCode": "0x61",
    "BriefDescription": "L2 cache requests for non-coherent, non-cacheable LS sized reads.",
    "UMask": "0x20"
  },
  {
    "EventName": "l2_request_g2.ls_rd_sized",
    "EventCode": "0x61",

Annotation

Implementation Notes