tools/perf/pmu-events/arch/x86/amdzen6/l3-cache.json

File Facts

System

Linux kernel

Corpus path

tools/perf/pmu-events/arch/x86/amdzen6/l3-cache.json

Extension

.json

Size

5512 bytes

Lines

178

Domain

Support Tooling And Documentation

Bucket

tools

Inferred role

Support Tooling And Documentation: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

[
  {
    "EventName": "l3_lookup_state.l3_miss",
    "EventCode": "0x04",
    "BriefDescription": "L3 cache misses.",
    "UMask": "0x01",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_lookup_state.l3_hit",
    "EventCode": "0x04",
    "BriefDescription": "L3 cache hits.",
    "UMask": "0xfe",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
    "EventCode": "0x04",
    "BriefDescription": "L3 cache requests for all coherent accesses.",
    "UMask": "0xff",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_xi_sampled_latency.dram_near",
    "EventCode": "0xac",
    "BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in the same NUMA node.",
    "UMask": "0x01",
    "EnAllCores": "0x1",
    "EnAllSlices": "0x1",
    "SliceId": "0x3",
    "ThreadMask": "0x3",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_xi_sampled_latency.dram_far",
    "EventCode": "0xac",
    "BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in a different NUMA node.",
    "UMask": "0x02",
    "EnAllCores": "0x1",
    "EnAllSlices": "0x1",
    "SliceId": "0x3",
    "ThreadMask": "0x3",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_xi_sampled_latency.near_cache",
    "EventCode": "0xac",
    "BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of another CCX in the same NUMA node.",
    "UMask": "0x04",
    "EnAllCores": "0x1",
    "EnAllSlices": "0x1",
    "SliceId": "0x3",
    "ThreadMask": "0x3",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_xi_sampled_latency.far_cache",
    "EventCode": "0xac",
    "BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of another CCX in a different NUMA node.",
    "UMask": "0x08",
    "EnAllCores": "0x1",
    "EnAllSlices": "0x1",
    "SliceId": "0x3",
    "ThreadMask": "0x3",
    "Unit": "L3PMC"
  },
  {
    "EventName": "l3_xi_sampled_latency.ext_near",
    "EventCode": "0xac",
    "BriefDescription": "Average sampled latency for L3 requests where data is returned from extension memory (CXL) in the same NUMA node.",

Annotation

• Atlas domain: Support Tooling And Documentation / tools.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.