tools/perf/pmu-events/arch/x86/arrowlake/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/arrowlake/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/arrowlake/cache.json
Extension
.json
Size
95588 bytes
Lines
2109
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ANY",
        "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_lowpower"
    },
    {
        "BriefDescription": "Counts the number of cache lines replaced in L0 data cache.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.L0_REPLACEMENT",
        "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cachelines replaced into the L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.L1_REPLACEMENT",
        "PublicDescription": "Counts cachelines replaced into the L1 d-cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },

Annotation

Implementation Notes