tools/perf/pmu-events/arch/x86/bonnell/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/bonnell/cache.json

File Facts

System: Linux kernel
Corpus path: tools/perf/pmu-events/arch/x86/bonnell/cache.json
Extension: .json
Size: 22135 bytes
Lines: 747
Domain: Support Tooling And Documentation
Bucket: tools
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

[
    {
        "BriefDescription": "L1 Data Cacheable reads and writes",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.ALL_CACHE_REF",
        "SampleAfterValue": "2000000",
        "UMask": "0xa3"
    },
    {
        "BriefDescription": "L1 Data reads and writes",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.ALL_REF",
        "SampleAfterValue": "2000000",
        "UMask": "0x83"
    },
    {
        "BriefDescription": "Modified cache lines evicted from the L1 data cache",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.EVICT",
        "SampleAfterValue": "200000",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "L1 Cacheable Data Reads",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.LD",
        "SampleAfterValue": "2000000",
        "UMask": "0xa1"
    },
    {
        "BriefDescription": "L1 Data line replacements",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.REPL",
        "SampleAfterValue": "200000",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Modified cache lines allocated in the L1 data cache",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.REPLM",
        "SampleAfterValue": "200000",
        "UMask": "0x48"
    },
    {
        "BriefDescription": "L1 Cacheable Data Writes",
        "Counter": "0,1",
        "EventCode": "0x40",
        "EventName": "L1D_CACHE.ST",
        "SampleAfterValue": "2000000",
        "UMask": "0xa2"
    },
    {
        "BriefDescription": "Cycles L2 address bus is in use.",
        "Counter": "0,1",
        "EventCode": "0x21",
        "EventName": "L2_ADS.SELF",
        "SampleAfterValue": "200000",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "All data requests from the L1 data cache",
        "Counter": "0,1",
        "EventCode": "0x2C",
        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",

Annotation

Atlas domain: Support Tooling And Documentation / tools.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.