tools/perf/pmu-events/arch/x86/broadwell/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/broadwell/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/broadwell/cache.json
Extension
.json
Size
104942 bytes
Lines
2729
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "L1D data line replacements",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "L1D miss outstandings duration in cycles",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "AnyThread": "1",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Not rejected writebacks that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x27",
        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
        "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x50"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "UMask": "0x7"
    },
    {
        "BriefDescription": "L2 cache lines in E state filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xF1",

Annotation

Implementation Notes