tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json
Extension
.json
Size
2946 bytes
Lines
69
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "Counter": "0,1",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
        "Counter": "0",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
        "Counter": "0",
        "CounterMask": "1",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
        "Counter": "0",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
        "PerPkg": "1",
        "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
        "PerPkg": "1",
        "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "ARB"
    }
]

Annotation

Implementation Notes