tools/perf/pmu-events/arch/x86/broadwellde/frontend.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
Extension
.json
Size
15522 bytes
Lines
268
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "Counter": "0,1,2,3",
        "EventCode": "0xe6",
        "EventName": "BACLEARS.ANY",
        "SampleAfterValue": "100003",
        "UMask": "0x1f"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
        "Counter": "0,1,2,3",
        "EventCode": "0xAB",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.  MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.HIT",
        "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.IFDATA_STALL",
        "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE.MISSES",
        "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
        "Counter": "0,1,2,3",
        "CounterMask": "4",
        "EventCode": "0x79",
        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
        "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
        "SampleAfterValue": "2000003",
        "UMask": "0x18"
    },
    {
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x79",
        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
        "PublicDescription": "This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
        "SampleAfterValue": "2000003",
        "UMask": "0x18"
    },
    {
        "BriefDescription": "Cycles MITE is delivering 4 Uops",
        "Counter": "0,1,2,3",
        "CounterMask": "4",
        "EventCode": "0x79",

Annotation

Implementation Notes