tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
Extension
.json
Size
121577 bytes
Lines
3213
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "LLC_MISSES.MEM_READ",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
        "ScaleUnit": "64Bytes",
        "UMask": "0x3",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
        "Counter": "0,1,2,3",
        "EventCode": "0x4",
        "EventName": "LLC_MISSES.MEM_WRITE",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
        "ScaleUnit": "64Bytes",
        "UMask": "0xc",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count; Activate due to Write",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_M_ACT_COUNT.BYP",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count; Activate due to Read",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_M_ACT_COUNT.RD",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count; Activate due to Write",
        "Counter": "0,1,2,3",
        "EventCode": "0x1",
        "EventName": "UNC_M_ACT_COUNT.WR",
        "PerPkg": "1",
        "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "ACT command issued by 2 cycle bypass",
        "Counter": "0,1,2,3",
        "EventCode": "0xA1",
        "EventName": "UNC_M_BYP_CMDS.ACT",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CAS command issued by 2 cycle bypass",
        "Counter": "0,1,2,3",
        "EventCode": "0xA1",
        "EventName": "UNC_M_BYP_CMDS.CAS",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "iMC"

Annotation

Implementation Notes