tools/perf/pmu-events/arch/x86/clearwaterforest/pipeline.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/clearwaterforest/pipeline.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/clearwaterforest/pipeline.json
Extension
.json
Size
5838 bytes
Lines
116
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for. Available PDIST counters: 0,1",
        "SampleAfterValue": "1000003"
    },
    {
        "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0,1",
        "SampleAfterValue": "1000003"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.CORE",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.CORE_P",
        "SampleAfterValue": "1000003"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
        "Counter": "Fixed counter 2",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "SampleAfterValue": "1000003",
        "UMask": "0x3"
    },
    {
        "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
        "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "SampleAfterValue": "1000003"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
        "Counter": "Fixed counter 0",
        "EventName": "INST_RETIRED.ANY",
        "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {

Annotation

Implementation Notes