tools/perf/pmu-events/arch/x86/elkhartlake/cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
Extension
.json
Size
72563 bytes
Lines
1285
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.",
        "Counter": "0,1,2,3",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ANY",
        "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basis.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
        "Counter": "0,1,2,3",
        "EventCode": "0x30",
        "EventName": "L2_REJECT_XQ.ANY",
        "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basis.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.HIT",
        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.REJECTS",
        "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x41"
    },

Annotation

Implementation Notes