tools/perf/pmu-events/arch/x86/elkhartlake/memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
Extension
.json
Size
32728 bytes
Lines
662
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
        "Counter": "0,1,2,3",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "SampleAfterValue": "20003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
        "PEBS": "1",
        "PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
        "PEBS": "1",
        "PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts all code reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000044",
        "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000044",
        "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000044",
        "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000044",
        "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",

Annotation

Implementation Notes