tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
Extension
.json
Size
15777 bytes
Lines
283
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
        "SampleAfterValue": "200003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
        "SampleAfterValue": "2000003",
        "UMask": "0x80"
    },

Annotation

Implementation Notes