tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json

Source file repositories/reference/linux-study-clean/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json

File Facts

System
Linux kernel
Corpus path
tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json
Extension
.json
Size
366406 bytes
Lines
7548
Domain
Support Tooling And Documentation
Bucket
tools
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

[
    {
        "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken",
        "Counter": "0,1,2,3",
        "EventCode": "0x57",
        "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.",
        "UMask": "0x2",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "CHA to iMC Bypass : Not Taken",
        "Counter": "0,1,2,3",
        "EventCode": "0x57",
        "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
        "UMask": "0x4",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "CHA to iMC Bypass : Taken",
        "Counter": "0,1,2,3",
        "EventCode": "0x57",
        "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.",
        "UMask": "0x1",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "CHA Clockticks",
        "Counter": "0,1,2,3",
        "EventCode": "0x01",
        "EventName": "UNC_CHA_CLOCKTICKS",
        "PerPkg": "1",
        "PublicDescription": "Number of CHA clock cycles while the event is enabled",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "CMS Clockticks",
        "Counter": "0,1,2,3",
        "EventCode": "0xc0",
        "EventName": "UNC_CHA_CMS_CLOCKTICKS",
        "PerPkg": "1",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops",
        "Counter": "0,1,2,3",
        "EventCode": "0x33",
        "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
        "UMask": "0xf2",
        "Unit": "CHA"
    },
    {
        "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop",
        "Counter": "0,1,2,3",
        "EventCode": "0x33",
        "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",

Annotation

Implementation Notes